The present invention relates to integrated circuit design, and more specifically, to memory element graph-based placement in integrated circuit design.
The process of creating an integrated circuit (IC), referred to as very large scale integration (VLSI) or chip design, includes many steps, some of which are repeated iteratively. Generally, combinational logic gates and memory elements (i.e., latches, flip-flops) are integrated into a process referred to as logic synthesis to implement the desired functionality of the IC. One of the results of the logic synthesis is a netlist that defines the connectivity among the various logic gates and memory elements that make up the IC. This logic synthesis is ultimately transitioned into a layout of physical components in an arrangement that considers the timing, congestion, and power usage constraints of the IC design. Processes that are performed iteratively as part of this transition from the logic design to the physical layout are referred to as physical synthesis. Physical synthesis includes placement (i.e., defining the location of cells), clock and timing optimization (i.e., ensuring that timing constraints are met based on the location of cells and the resulting wire lengths of interconnects), and routing (i.e., defining paths for the wires interconnecting cells). The goal of physical synthesis is to generate a layout that meets timing, congestion, and power metrics.